This invention relates generally to the design and manufacture of integrated circuits, and more particularly to the design and manufacture of input/output (I/O) circuits within the integrated circuit.
A typical integrated circuit (IC) includes a circuit die upon which a plurality of circuit components are provided to form a primary circuit and a plurality of dedicated input, output, or input/output (I/O) circuits. The I/O circuits can be used to input and output I/O signals, such as control, address and data signals. A typical I/O circuit includes an I/O cell and a conducting pad. The conducting pad is usually a bonding pad that can, for example, be coupled to an I/O pin with a bonding wire during manufacture.
As is known to those skilled in the art, there are usually only a limited number of I/O circuits and I/O pins that can be efficiently supported for a given die or package size. Thus, if the number of required I/O signals exceeds the number of available I/O circuits or pins that are available for a specific die or package size, the die and/or package will typically need to be increased in size to accommodate the additional I/O requirements. Increasing the size of the die, however, tends to increase the costs associated with manufacture of the IC, and can lead to "wasted" space on the die and unused I/O pins in the package. Furthermore, additional space may be required for the resulting larger IC within an intended system circuit, e.g., a printed circuit board.
Alternatively, when additional I/O circuits are required, the area on the die allocated to the primary circuit can be reduced thereby providing additional space for the additional I/O circuits. However, this solution can also lead to wasted space on the die as a result of common design/layout practices which usually call for placing a the I/O circuits in rows around or near the outer edges of the die, and the primary circuit, in a more or less rectangular or square area, near the center of the die.
Another potential solution is to separate a desired circuit into two or more portions and to design separate integrated circuits for each portion. While this can have its advantages, such as allowing for modular designs or specialized processes, it also tends to increase the number of components and space required in the final system. Moreover, this can result in higher manufacturing costs.
Consider, for example, FIG. 1a which is a block diagram illustrating a typical interface 10 that includes several integrated circuits each having one or more I/O circuits therein. These integrated circuits and the lines connecting each of them represent a portion of a data network, such as one that interconnects and provides data communication services between a computer and other related devices.
As shown, interface 10 is a typical implementation of an IEEE-1394 standard bus. Implementations, such as this, are well known to those skilled in the art, and can, for example, be used to support data transfer rates of 100, 200, and 400 Mbits/second between a plurality of devices.
IEEE-1394 specification P1394 draft 8.0 Version 2, which is available from IEEE of Piscataway, N.J., and which is incorporated herein by reference, defines a three-layered transport system consisting of a physical layer, a link layer and a transaction layer. Basically, the physical layer provides the signals required by an IEEE-1394 bus, the link layer takes the raw data from the physical layer and formats it into recognizable data packets, and the transaction layer takes the data packets from the link layer and presents them to an application.
As is known in the art, it is common to implement some of these different layers in separate, dedicated integrated circuits because of their unique functions, circuits, and I/O requirements. For example, the physical layer, which usually includes analog transceivers for sending and receiving I/O signals over the 4 (or greater) wires associated with the IEEE-1394 bus, can be implemented in a physical layer chip, or "PHY chip". In addition to sending and receiving I/O signals, a typical PHY chip can also perform system initialization, bus arbitration, and the associated handshaking required to transmit data in a over the bus. An example of a PHY chip is the IBM 21S750PFB available from International Business Machines (IBM) Corporation of White Plains, N.Y.
A "LINK chip", which is usually a digital logic circuit, is essentially the hardware implementation of the link layer. A LINK chip can also implement portions of the transaction layer, as well. A typical LINK chip basically provides isochronous (e.g., voice and video) data transfers, and forms, transmits and receives formatted data packets. An example of a typical LINK chip is the TI F643950 available from Texas Instruments Incorporated, of Dallas, Tex.
Referring to FIG. 1a, interface 10 includes a logic circuit 12, a LINK chip 14, a PHY chip 16, and an IEEE-1394 bus 18. Logic circuit 12 can, for example, represent the interface circuitry within a device such as a computer, a scanner, a printer, a disc controller, tape drive, or other like device that sends and receives various data in the form of I/O signals over bus 18.
As shown, LINK chip 14 is coupled to exchange I/O signals with logic circuit 12 over lines 20, and with PHY chip 16 over lines 22. PHY chip 16 is coupled to exchange I/O signals with LINK chip 14 over lines 22, and with external circuits or devices (not shown) over bus 18. The external circuits or devices can, for example, be similar to those represented by logic circuit 12 and can include the same or similar circuits as interface 10, as well.
One drawback with interface 10, however, is the high number of integrated chips required to provide an interface between logic circuit 12 and bus 18. In particular, for many applications it would be advantageous to combine LINK chip 14 and PHY chip 16 in a single integrated circuit. Unfortunately, this has not proven an easy task due to a number of different design issues. One of the design issues is the number and types of I/O circuits, and the space limitations for a given die. For example, unlike a LINK chip, a PHY chip typically includes I/O circuits that are dedicated for driving I/O signals over bus 18 in a differential mode. Thus, any similarly configured LINK/PHY chip hybrid, or combination, would therefore be required to provide this additional differential I/O capability.
FIG. 1b is a diagrammatic illustration of an integrated circuit 40 that has additional I/O circuits that are capable of supplying a given conducting pad with either a normal or a differential I/O signal. Integrated circuit 40 includes a die 40 having a primary circuit 44, and a plurality of I/O circuits 46 formed in different areas, thereon. As depicted, a subset 48 of the plurality of I/O circuits 46 are typically formed in a row along one or more sides of die 42. Each I/O circuit includes a conducting pad 50, a main I/O cell 52 and a secondary I/O cell 54. Main I/O cell 52 can, for example, include the components that function to transfer normal I/O signals between primary circuit 44 and the main I/O cell's associated conducting pad 50. Such I/O cells are well known in the art, and are commonly referred to as single-ended I/O cells. Secondary I/O cell 54 can, for example, include the components that function to transfer differential (as opposed to single-ended) I/O signals between primary circuit 44 and the secondary I/O cell's associated conducting pad 50. Such I/O cells are well known in the art, and are commonly referred to as differential I/O cells. Of course, depending upon the design, one or more of the main I/O cells could be differential I/O cells, and one or more of the secondary I/O cells could be single-ended I/O cells, as well.
Unfortunately, one drawback to adding the secondary I/O cells is that some of the secondary I/O cells may not be used by the final integrated circuit, or for that matter, even be provided with components during manufacture. For example, while there are I/O circuits within PHY chip 16 that are single-ended, and others that are differential, FIG. 1b also reflects that there are several "unused" secondary I/O cells 56 (i.e., having an "X" drawn through them). As a result of extending the length of I/O circuits (i.e., to create space for a secondary I/O cell) in one or more of the I/O circuits in a row, the amount of remaining space provided for primary circuit 44 will typically be reduced. Moreover, there is the possibility that some of the space consumed by the I/O circuit expansion, such as unused secondary I/O cells 56, will simply be wasted.
Therefore, what is desired are more efficient methods and apparatuses for providing I/O circuits for use with a combined LINK/PHY circuit on a single circuit die, wherein the I/O circuits are capable of supporting single-ended and differential I/O signaling modes without significantly reducing the available space on a circuit die for the combined LINK/PHY circuit.